1. Field of the Invention
This invention relates generally to semiconductor fabrication, and, more particularly, to reserving a processing tool in a semiconductor fabrication facility.
2. Description of the Related Art
A semiconductor fabrication facility typically includes numerous processing tools used to fabricate semiconductor devices. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Semiconductor fabrication facilities generally include more than one example of each type of processing tool and each processing tool may include multiple chambers. For example, a semiconductor fabrication facility may include several photolithography steppers, which may include more than one chamber for processing wafers. A semiconductor fabrication facility may also include several etch tools, one or more polishing tools, one or more metrology tools, one or more electrical testing tools, and the like.
Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular product design and/or operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper or module may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. Since the semiconductor fabrication facility includes numerous examples of each type of processing tool, the semiconductor fabrication facility may be capable of concurrently processing numerous wafers and/or wafer lots. For example, the semiconductor fabrication facility may concurrently process several wafer lots in parallel by providing the wafer lots to a corresponding number of processing tools, e.g., photolithography steppers and/or chambers therein, which may then process the wafer lots according to an operating recipe associated with the product to be formed in or on the wafer lots.
Once the wafer lots have completed a processing step, they may be provided to one or more processing tools for additional processing. For example, after being processed in one or more photolithography steppers and/or chambers therein, a group of partially processed wafer lots may be provided to a group of etch tools. Each of the partially processed wafer lots may be provided to one of the etch tools based on a scheduling algorithm associated with the etch tools. For example, the scheduling algorithm may determine which of the partially processed wafer lots to provide to each of the etch tools based on priorities associated with the partially processed wafer lots, tool availability, operating recipes associated with the wafer lots, and the like. Conventional scheduling algorithms only assign wafer lots to the associated processing tools when the wafer lots are ready to be processed by the associated processing tools. For example, the scheduling algorithm associated with the etch tools may schedule wafer lots for processing by the etch tools after the wafer lots have completed processing in one or more photolithography steppers.
Scheduling wafer lots for processing by a processing tool in a second group of tools only after processing by a processing tool in a first group of tools has completed may increase cycle times and/or reduce tool utilization. For example, if a tool exception occurs in one of the processing tools in the second group of tools, one or more other tools in the second group of tools may need to be converted to perform the operations that would have been performed by the unavailable processing tool. Furthermore, one or more of the wafer lots may need to be rerouted to other processing tools in the second group of tools. Consequently, the wafer lots that have been processed in the first group of tools may be delayed while these, or other, operations are performed. Accordingly, the cycle time for the processing line including the first and second tool groups may be increased. For another example, additional processing tools may come online, which may permit additional wafer lots to be processed. However, the additional processing tools may be underutilized because the scheduling algorithms associated with processing tools at earlier stages in the processing line may be unaware of the additional processing capacity associated with the additional processing tools.
The independent nature of the various scheduling algorithms may make it difficult to coordinate operations of the processing tool groups to achieve global goals of the semiconductor fabrication facility. For example, the number of each type of product formed by the semiconductor fabrication facility, as well as the deadlines for producing these products, may be determined by forces such as current market demand for each product, shipping commitments made to clients, lot requests by research and development teams, and the like. In a conventional semiconductor fabrication facility, engineers manually configure the various scheduling algorithms and associated processing tools to attempt to meet the global goals. This process is time-consuming, may reduce the efficiency of the semiconductor fabrication facility, and is not always successful. Furthermore, if any of the forces that determine the global goals should change, the various scheduling algorithms must be manually reconfigured to attempt to meet the changing goals.
The present invention is directed to addressing the effects of one or more of the problems set forth above.